Power gating is a technique for low power applications. By power gating, a high speed chip can keep running in high frequency, while blocks not in use are powered-off to save power. This can be achieved using a semiconductor FET (field effect transistor) switch, which requires extremely small turn-on resistance (Ron) and high ratio of current on to current off. Chip IR drop is preferably as small as possible. When device dimension shrinks, front-end-of-line (FEOL) resistance rises due to diffusion, and contact area decreases. Also, back-end-of-line (BEOL) resistance rises due to shrinking metal conductor width and via size.